The more delicate a process has become, the more the number of transient errors has become. A typical example of such a transient error is a soft error. A soft error was a problem related to outer space or an SRAM. However, recently, even on earth, it has become necessary to have countermeasures against a soft error. A main cause of generation of a soft error on earth is a high-energy neutron.
As illustrated in FIG. 9, a collision of a high-energy neutron against an Si atom of a substrate generates a secondary ion. In a case where the secondary ion passes by a diffusion layer, electrons or holes gather in the diffusion layer because of (i) diffusion or (ii) occurrence of a drift due to an electric field of a depletion layer. Such electrons or holes change an electric charge of a drain, and, as a result, an output is inverted.
Depending on where a collision of a high-energy neutron occurs, a soft error is classified into the following three types: SEU (Single Event Upset), SET (Single Event Transient), and MCU (Multiple Cell Upset). SEU is such an error that a high-energy neutron collides with an FF (flip-flop) or an SRAM and therefore directly inverts retained data (see (a) of FIG. 10). SET is such an error that a high-energy neutron collides with a combinational circuit and therefore generates a pulse (see (b) of FIG. 10). MCU is such an error that, in an SRAM having a high integration degree, a plurality of pieces of data, retained by a plurality of SRAMs, are inverted at one time (see (c) of FIG. 10).
An error ratio of an FF due to SEU has increased up to approximately 1e-3 FIT. “FIT” is an expected value of the number of times that an error occurs in 1e9 hour. In a case where a chip employing one million FFs is used, one error might occur in approximately 100 years. Note that an FF and an SRAM are identical with each other in an error ratio due to SEU.
In the case of SET, an error occurs in such a manner that a pulse is taken by a latch circuit. As such, an error ratio due to SET is smaller than the error ratio due to SEU. However, in order to build a circuit having a high resistance to a soft error, it is necessary to have countermeasures against not only an error due to SEU but also an error due to SET. A dual modular FF employing a redundant FF is used in order to reduce error ratios due to SEU and SET. Examples of a circuit configuration employing the multiple modular FF encompass a TMR (Triple Modular Redundancy) and a delay insertion TMR (DTMR).
FIG. 11 is a view illustrating a configuration of a flip-flop circuit FF 50, which is a general TMR. The flip-flop circuit FF 50 includes (i) three master latch circuits LAT 51, LAT 52, and LAT 53, (ii) three slave latch circuits LAT 54, LAT 55, and LAT 56, (iii) three majority circuits VOT 51, VOT 52, and VOT 53, and (iv) a single inverter circuit INV 51. Input terminals of the master latch circuits LAT 51, LAT 52, and LAT 53 receive input data IN 0, input data IN 1, and input data IN 2, respectively, which are supplied from three combinational circuits COMB 51, COMB 52, and COMB 53, respectively. Further, the slave latch circuits LAT 54, LAT 55, and LAT 56 output output data OUT 0, output data OUT 1, and output data OUT 2, respectively.
As mentioned above, the flip-flop circuit FF 50 has an arrangement in which a combination of a combinational circuit, a master latch circuit, a slave latch circuit, and a majority circuit is triplicated. With the arrangement, an error does not occur unless a plurality of latch circuits are inverted simultaneously. Accordingly, such an arrangement has a high resistance to an error. However, since not only a latch circuit and a majority circuit but also a combinational circuit is triplicated, a circuit size of the flip-flop circuit FF 50 becomes not less than three times larger than that of a general non-redundant FF. That is, the flip-flop circuit FF 50 has a large overhead in area.
FIG. 12 is a view illustrating a configuration of a flip-flop circuit FF 60, which is a general DTMR. The flip-flop circuit FF 60 includes (i) three master latch circuits LAT 61, LAT 62, and LAT 63, (ii) three slave latch circuits LAT 64, LAT 65, and LAT 66, (iii) a single majority circuit VOT 61, (iv) two delay circuits DEL 61 and DEL 62, and (v) a single inverter circuit INV 61. Input data IN is supplied from a combinational circuit COMB 61 to both an input terminal of the master latch circuit LAT 61 and an input terminal of the delay circuit DEL 61. Further, the majority circuit VOT 61 outputs output data OUT.
As mentioned above, the flip-flop circuit FF 60 does not employ an arrangement in which a combinational circuit is triplicated but such an arrangement that an SET pulse generated in the combinational circuit COMB 61 is removed by the two delay circuits DEL 61 and DEL 62. With the arrangement, an SET pulse generated in the majority circuit VOT 61 is also removed by delay circuits located downstream. For this reason, it is not necessary to triplicate the majority circuit VOT 61. Accordingly, a circuit size of the flip-flop circuit FF 60 is smaller than that of the flip-flop circuit FF 50, which is a TMR. However, the flip-flop circuit FF 60 has a problem that the two delay circuits DEL 61 and DEL 62 cause an increase in delay time.
Moreover, since both the flip-flop circuit FF 50 and the flip-flop circuit FF 60 employ a majority circuit, there is a problem that a resistance to an error due to MCU is low. Specifically, in a case where (i) two master latch circuits are inverted among three master latch circuits or (ii) two slave latch circuits are inverted among three slave latch circuits, an output is also inverted.
There has been proposed such a delay insertion DMR (DDMR, BISER) that, in the flip-flop circuit FF 50 or the flip-flop circuit FF 60, a C-element circuit and a weak keeper circuit are employed. (a) of FIG. 13 is a view illustrating a configuration of a flip-flop circuit FF 70, which is a BISER, and (b) of FIG. 13 is a view illustrating a configuration of a C-element circuit of the flip-flop circuit FF 70.
As illustrated in (a) of FIG. 13, the flip-flop circuit FF 70 includes (i) two master latch circuits LAT 71 and LAT 72, (ii) two slave latch circuits LAT 73 and LAT 74, (iii) two C-element circuits CE 71 and CE 72, (iv) two weak keeper circuits WK 71 and WK 72, (v) a single delay circuit DEL 71, and (vi) a single inverter circuit INV 71. Input data IN is supplied from a combinational circuit COMB 71 to both an input terminal of the master latch circuit LAT 71 and an input terminal of the delay circuit DEL 71.
The weak keeper circuit WK 71 is constituted by two inverter circuits INV 72 and INV 73. Similarly, the weak keeper circuit WK 72 is constituted by two inverter circuits INV 74 and INV 75. With the arrangement, the weak keeper circuits WK 71 and WK 72 retain output data supplied from the C-element circuits CE 71 and CE 72, respectively.
As illustrated in (b) of FIG. 13, each of the C-element circuits includes two PMOS transistors MP 1 and MP 2 and two NMOS transistors MN 1 and MN 2. The transistors MP 1 and MP 2 are connected to each other in series between a power-supply electric potential VCC and an output node N3, and the NMOS transistors MN 1 and MN 2 are connected to each other in series between the output node N 3 and a ground potential VSS. Further, each of gates of the transistors MP 1 and MN 2 is connected to a first input node N 1 of the C-element circuit, and each of gates of the transistors MP 2 and MN 1 is connected to a second input node N 2 of the C-element circuit. With the arrangement, in a case where a value inputted into the input node N 1 and a value inputted into the input node N 2 are different from each other, the C-element circuit retains an immediately previous value.
Accordingly, with the flip-flop circuit FF 70, an error does not occur even in a case where one of data retained by the master latch circuit LAT 71 and data retained by the master latch circuit LAT 72 is inverted. Further, an SET pulse generated in the combinational circuit COMB 71 is removed by the delay circuit DEL 71. Furthermore, since (i) a circuit size of the flip-flop circuit FF 70 is smaller than that of a DTMR, and (ii) the flip-flop circuit FF 70 has a single delay circuit, a delay time is not as much as that of the DTMR.
However, the flip-flop circuit FF 70 illustrated in FIG. 13 has such a disadvantage that the flip-flop circuit FF70 is vulnerable to an error due to an SET pulse generated in the C-element circuit. Specifically, as illustrated in FIG. 14, in a case where a high-energy neutron collides with the C-element circuit and generates an SET pulse, such an SET pulse is latched by both the two slave latch circuits LAT 73 and LAT 74. This causes an output of the downstream C-element circuit CE 72 to be inverted. Further, the flip-flop circuit FF 70 has such a problem that, although a resistance to an error is high when a clock frequency is low, a resistance to an error decreases with an increase in clock frequency.
In view of these, the inventors of the present invention has proposed a D3MR (Double Delayed DMR) and an ED2MR (Enhanced Delayed DMR) as a DMR which is further improved in resistance to an error (Non-Patent Literature 1).
FIG. 15 is a view illustrating a configuration of a flip-flop circuit FF 80, which is a D3MR. The flip-flop circuit FF 80 has such an arrangement that, in the flip-flop circuit FF 70 illustrated in FIG. 13, a delay circuit DEL 81 is provided upstream of an input terminal of the slave latch circuit LAT 74. With the arrangement, it is possible to remove an SET pulse generated in the C-element circuit CE 71 by use of the delay circuit DEL 81.
FIG. 16 is a view illustrating a configuration of a flip-flop circuit FF 90, which is an ED2MR. The flip-flop circuit FF 90 has such an arrangement that, in the flip-flop circuit FF 70 illustrated in FIG. 13, (i) a C-element circuit CE 91 and a weak keeper circuit WK 91 are further included, (ii) the C-element circuit CE 71 and the weak keeper circuit WK 71 are connected to the slave latch circuit LAT 73, and (iii) the C-element circuit CE 91 and the weak keeper circuit WK 91 are connected to the slave latch circuit LAT 74. The weak keeper circuit WK 91 is constituted by two inverter circuits INV 91 and INV 92, in the same manner as the weak keeper circuits WK 71 and WK 72.
The flip-flop circuit FF 90 has an arrangement in which a combination of a C-element circuit and a weak keeper circuit, provided between master latch circuits and slave latch circuits, are duplicated. With the arrangement, even in a case where an SET pulse is generated in one of the C-element circuits CE 71 and CE 91, an output of the downstream C-element circuit CE 72 is not inverted. This makes it possible to increase a resistance to an error due to an SET pulse generated in the C-element circuit.